BOUNDARY SCAN TEST
Boundary scan also known as JTAG offers a lower cost and faster deployment alternative to In-circuit and functional tests. Arxtron Technologies offers a full development service using Keysight x1149 Boundary Scan Analyzer.
HARDWARE
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Structural test such as opens and shorts
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In-System Programming for devices such as FPGAs and CPLDs.
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PROM programming (Programmable Read-Only Memory)
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Memory verification tests on devices such as DDR3, DDR4
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Fully compliant to the IEEE 1149.1 Boundary Scan standard,
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Cover-Extend Technology enables test coverage to go beyond just IEEE 1149.1 devices – to also include connectors, sockets and non IEEE1149.1 device
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Supports IEEE 1149.6 standard for AC-coupled bus lines.
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Supports in-built scan chain linke to join multiple scan chains
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Supports IEEE 1687 standard
DEVELOPMENT
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JTAG Infrastructure test
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Opens and Shorts
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Silicon nails testing (a.k.a Cluster test)
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ISP programming (CPLD, PROM)
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IEEE 1149.1 and IEEE 1149.6
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CoverExtendTM for ICs, connectors and sockets.
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Scan Chain Linker for multi-board systems
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Intel SVT Technology support
NPI & DFT
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Design For Test Analysis
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Test Point Reduction (TPR) Report
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Multi chain generation
