BOUNDARY SCAN TEST

Boundary scan also known as JTAG offers a lower cost and faster deployment alternative to In-circuit and functional tests. Arxtron Technologies offers a full development service using Keysight x1149 Boundary Scan Analyzer.

HARDWARE

  • Structural test such as opens and shorts
  • In-System Programming for devices such as FPGAs and CPLDs.
  • PROM programming (Programmable Read-Only Memory)
  • Memory verification tests on devices such as DDR3, DDR4
  • Fully compliant to the IEEE 1149.1 Boundary Scan standard,
  • Cover-Extend Technology enables test coverage to go beyond just IEEE 1149.1 devices – to also include connectors, sockets and non IEEE1149.1 device
  • Supports IEEE 1149.6 standard for AC-coupled bus lines.
  • Supports in-built scan chain linke to join multiple scan chains
  • Supports IEEE 1687 standard
Automated Test Systems
boundary scan chart

DEVELOPMENT

  • JTAG Infrastructure test
  • Opens and Shorts
  • Silicon nails testing (a.k.a Cluster test)
  • ISP programming (CPLD, PROM)
  • IEEE 1149.1 and IEEE 1149.6
  • CoverExtendTM for ICs, connectors and sockets.
  • Scan Chain Linker for multi-board systems
  • Intel SVT Technology support

NPI & DFT

  • Design For Test Analysis
  • Test Point Reduction (TPR) Report
  • Multi chain generation
keysight scan analyzer software
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