DESIGN FOR TESTABILITY & FEASIBILITY STUDIES

Arxtron Technologies has developed a thorough design for testability (DFT) process over the years. Design teams from renowned OEMs in the Telecom, Medical and automotive industries have used Arxtron’s DFT recommendations to maximize and/or optimize their In-circuit (ICT) and boundary scan test coverage.

DESIGN FOR TESTABILITY

  • Layout analysis
  • Test access analysis
  • Fixture analysis
  • Strain simulation analysis
  • Design topology analysis (Schematics)
  • Critical access recommendations
  • Limited access coverage
  • Test point reduction techniques
  • Smart power requirements analysis
  • Boundary scan requirements analysis
  • Boundary scan chain analysis
  • Power sequencing requirements
  • Flash programming requirements
  • Flash programming algorithm development
  • Test coupon analysis
  • Predictive coverage
  • DFT report and design reviews

FEASIBILITY STUDIES

  • BSDL verification
  • Boundary Scan compliance verification
  • Boundary scan register integrity
  • ATE managed power sequencing
  • Boundary scan cluster test verification
  • Smart power PMIC programming
  • ISP programming at ICT (MCU, NAND, eMMC)